1. Field of the Invention
The invention relates to a digital phase-locked loop circuit, more particularly to a digital phase-locked loop circuit that requires a relatively small circuit layout.
2. Description of the Related Art
Equalizers are usually built in control chips for optical disk drives suitable for CD-ROM, CD-R, CD-RW and DVD-ROM applications, and serve to amplitude equalize radio frequency signals generated by an optical pickup heads when reading an optical disk. Therefore, it is important to stabilize a −3 dB frequency (fE) of an equalizer filter so as not to affect post-processing by a digital signal processor.
FIG. 1 illustrates a control loop composed of a conventional phase-locked loop circuit 1 and a voltage controlled oscillator 2 for adequately adjusting a control voltage signal (vin) inputted to an equalizer filter 6 so as to stabilize a −3 dB frequency (fE) of the equalizer filter 6. The conventional phase-locked loop circuit 1 serves to generate the control voltage signal (vin) that is used to enable the voltage controlled oscillator 2 to generate a target frequency output (fB). The conventional phase-locked loop circuit 1 includes a frequency divider 11 for frequency dividing an output frequency (fo) outputted by the voltage controlled oscillator 2 in response to the control voltage signal (vin), a phase comparator 12 for phase comparing the output the frequency divider 11 with the target frequency output (fB) and for outputting an error signal (Te) according to a phase difference therebetween, a charge pump 13 driven in response to the error signal (Te) and outputting a current output Io, and a low-pass filter 14, which includes a resistor (R0) and a capacitor (C0), for integrating the current output from the charge pump 13 and for outputting the control voltage signal (vin).
It is assumed that the −3 dB frequency (fE) of the equalizer filter 6 is represented by the following equation: fE=k1×vin, where k1 is a constant associated with electrical characteristics of electronic components in the equalizer filter 6 and changes with actual operating temperature conditions, and that the target frequency output (fB) is represented by the following equation: fB=k2×vin, where k2 is a constant associated with electrical characteristics of electronic components in the control loop and also changes with actual operating temperature conditions. Since a ratio of k1 and k2 almost does not change even at different operating temperature conditions, the control voltage signal (vin) generated by the conventional phase-locked loop circuit 1 can stabilize the −3 dB frequency (fE) of the equalizer filter 6.
However, in view of the above configuration, the frequency divider 11, the phase comparator 12 and the charge pump 13 require a relatively large layout area (about 280000 μm2) for fabrication.